technical data IN74HCT164A 8-b it s erial -i nput /p arallel -o utput s hift r esister ordering information IN74HCT164An plastic IN74HCT164Ad soic t a = -55 to 125 c for all packages high-performance silicon-gate cmos the IN74HCT164A m a y be used as a level converter for interfacing ttl or nmos outputs to high-speed cmos inputs. the IN74HCT164A is identical in pin out to the ls/als164. ? ttl/nmos-com patible input levels. ? outputs directly interface to cmos, nmos and ttl. ? operating voltage range: 4.5 to 5.5 v ? low input current: 1.0 a pin assignment function table input s o u t put s reset c lock a1 a2 q a q b ... q h l x x x l l ... l h x x no change h h d d q an ... q gn h d h d q an ... q gn d = data input x = don?t care q an - q gn = data shifted from the previous stage on a rising edge at the clock input. logic diagram pin 14 =v cc pin 7 = gnd rev. 00
IN74HCT164A maximum ratings * sy m b o l p a r a m e t e r v a l u e u n i t v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage tem p erature -65 to +150 c t l lead tem p erature, 1 m m from case for 10 seconds (plastic dip or soic package) 260 c * maxim u m ratings are those values bey ond which dam a ge to the device m a y occur. functional operation should be restricted to the recom m e nded operating conditions. +derating - plastic dip: - 10 m w / c from -55 to 125 c soic package: : - 7 m w / c from -55 to 125 c recommended operating conditions sy m b o l p a r a m e t e r m i n m a x u n i t v cc dc supply voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating tem p erature, all package ty pes -55 +125 c t r , t f input rise and fall tim e (figure 1) 0 500 ns this device contains protection circuitry to guard against dam a ge due to high static voltages or electric fields. however, precautions m u st be taken to avoid applications of any voltage higher than m a xim u m rated voltages to this high-im pe dance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs m u st alway s be tied to an appropr iate logic voltage level (e.g., either gnd or v cc ). unused outputs m u st be left open. rev. 00
IN74HCT164A dc electrical characteristics (voltages referenced to gnd) v c c guaranteed lim it sy m b o l p a r a m e t e r test c o n d i t i o n s v 25 c to -55 c 85 c 125 c unit v ih minim u m high- l e v e l i n p u t voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 v v il m a x i mu m l o w - l e v e l i n p u t voltage v out = v cc -0.1 v ? i out ? 20 a 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 v v oh minim u m high- l e v e l o u t p u t voltage v in =v ih or v il ? i out ? 20 a 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 v v in =v ih or v il ? i out ? 4.0 m a 4.5 3.98 3.84 3.7 v ol m a x i mu m l o w - l e v e l o u t p u t voltage v in =v ih ? i out ? 20 a 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v v in =v ih ? i out ? 4.0 m a 4.5 0.26 0.33 0.4 i in maxim u m i n p u t leakage current v in =v cc or gnd 5.5 0.1 1.0 1.0 a i cc m a x i mu m quiescent supply current (per package) v in =v cc or gnd i out =0 a 5.5 1 . 0 1 0 4 0 a ? i cc additional quiescent supply current v in = 2.4 v, any one input -55 c 2 5 c to 125 c ma v in =v cc or gnd, other inputs i out =0 a 5.5 2 . 9 2 . 4 rev. 00
IN74HCT164A ac electrical characteristics (v cc =5.0 v 10% , c l =50pf, input t r =t f =6.0 ns) g u a r a n t e e d lim i t sy m b o l p a r a m e t e r 25 c to -55 c 85 c 125 c unit f ma x maxim u m clock frequency (50% duty cy cle) (figures 1 and 4) 3 0 2 4 2 0 mhz t plh , t phl maxim u m propagation delay , clock to q (figures 1 and 4) 3 8 4 8 5 8 n s t phl maxim u m propagation delay , reset to q (figures 2 and 4) 4 1 5 2 6 3 n s t tlh , t thl maxim u m output transition tim e , any output (figures 1 and 4) 1 5 1 9 2 2 n s c in maxim u m input capacitance 10 pf power dissipation capacitance (per package) typical @25 c,v cc =5.0 v c pd used to determ ine the no-load dy nam i c power consum ption: p d =c pd v cc 2 f+i cc v cc 3 6 0 p f timing requirements (c l =50pf,input t r =t f =6.0 ns) g u a r a n t e e d lim i t sy m b o l p a r a m e t e r 25 c to -55 c 85 c 125 c unit t su minim u m setup tim e ,a1 or a2 to clock (figure 3) 7 8 9 n s t h m i n i mu m h o l d t i me , clock to a1 or a2 (figure 3) 5 5 5 n s t rec m i n i mu m r e c o v e r y t i me , reset inactive to clock (figure 2) 5 5 5 n s t w minim u m pulse width, reset (figure 2) 1 2 1 5 2 0 n s t w minim u m pulse width, clock (figure 1) 1 2 1 5 2 0 n s rev. 00
IN74HCT164A figure 1. switching waveform s figure 2. switching waveform s figure 3. switching waveforms figure 4. test circuit timing diagram ex panded logic diagram rev. 00
IN74HCT164A n s u f f i x p l as t i c di p (m s - 0 0 1 a a ) sy m b o l m i n m a x a 18. 67 19. 69 b 6. 1 7 . 1 1 c 5. 33 d 0. 36 0. 56 f 1. 14 1. 78 g h j 0 10 k 2. 92 3. 81 no t e s : l 7. 62 8. 26 1. d i m e n s i o n s ?a ?, ?b ? d o n o t i n cl u d e m o l d f l as h o r p r o t r u s i o n s . m 0. 2 0 . 3 6 m a x i m u m m o l d f l a s h o r p r o t r u s i o n s 0. 25 m m ( 0 . 010) p e r s i d e . n 0. 38 d su f f i x so i c (m s - 0 1 2 a b ) sy m b o l m i n m a x a 8. 55 8. 75 b 3. 8 4 c 1. 35 1. 75 d 0. 33 0. 51 f 0. 4 1 . 2 7 g h j 0 8 no t e s : k 0. 1 0 . 2 5 1. d i m e n s i o ns a a n d b d o no t i n c l ud e m o l d f l a s h o r p r ot r u s i on . m 0. 19 0. 25 2. m a x i m u m m o l d f l a s h o r p r o t r u s i o n 0. 15 m m ( 0 . 006) p e r s i d e p 5. 8 6 . 2 fo r a ; fo r b ? 0. 25 m m ( 0 . 010) p e r s i d e . r 0. 25 0. 5 d i me n s i o n , mm 1. 27 5. 27 2. 54 7. 62 d i me n s i o n , mm a b h c k c m j f m p g d r x 4 5 se a t i n g pl an e 0.2 5 ( 0 . 0 10 ) m t -t - 1 14 7 8 a b f g d l h se a t i n g pl a n e n k 0.25 ( 0 . 010) m t m j -t - c 1 14 7 8 rev. 00
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